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GS1575B / gs9075b hd-l inx? ii multi-rate sd i automatic reclocker 1 of 28 GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 www.gennum.com features GS1575B ? smpte 292m, 259m and 344m compliant ? supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 mb/s ? supports dvb-asi at 270mb/s ? pb-free and rohs compliant ? auto and manual mode s for rate selection ? standards indication in auto mode ? 4:1 input multiplexer ? loss of signal (los) output ? lock detect output ? on-chip input and output termination ? differential 50 inputs and outputs ? mute, bypass and autobypass functions ? sd/hd indication output to control gs1528a dual slew-rate cable driver ? single 3.3v power supply ? operating temperature range: 0c to 70c gs9075b ? smpte 259m and 344m compliant ? supports data rates of 143, 177, 270, 360, and 540mb/s ? supports dvb-asi at 270mb/s ? pb-free and rohs compliant ? auto and manual mode s for rate selection ? standards indication in auto mode ? 4:1 input multiplexer ? loss of signal (los) output ? lock detect output ? on-chip input and output termination ? differential 50 inputs and outputs ? mute, bypass and autobypass functions ? single 3.3v power supply ? operating temperature range: 0c to 70c applications GS1575B ? smpte 292m, smpte 259m and smpte 344m serial digital interfaces gs9075b ? smpte 259m and smpte 344m serial digital interfaces. description the GS1575B/9075b is a multi-ra te serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the GS1575B serial digital reclocker will recover the embedded clock signal and re-time the data from a smpte 292m, smpte 259m or smpte 344m compliant digital video signal. the gs9075b serial digital reclocker will recover the embedded clock signal and re-time the data from a smpte 259m or smpte 344m complian t digital video signal. the GS1575B/9075b removes th e high frequency jitter components from the bit-serial stream. input termination is on-chip for seamless matching to 50 transmission lines. an lvpecl compliant output interfaces seamlessly to the gs1578a/gs9078a ca ble driver. the GS1575B/9075b can operate in either auto or manual rate selection mode. in auto mode the device will automatically detect and lock onto incoming smpte sdi data signals at any supported rate. for single rate data systems, the GS1575B/9075b can be configured to operate in manual mode. in both modes, the device requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. in systems which require passing of non-smpte data rates, the GS1575B/9075b can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. the asi/177 input pin allows for manual selection of support of either 177mb/s or dvb-asi inputs. the GS1575B/9075b is pb-free , and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous sub-components are rohs compliant.
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 2 of 28 GS1575B functional block diagram gs9075b functional block diagram xtal+ xtal- xtal out- xtal out+ ddi_sel[1:0] ddi 1 ddi 2 ddi 3 ddi 0 lf+ lf- kbb ddo_mute ddo/ddo autobypass bypass ld auto/man ss[2:0] asi/177 xtal osc buffer data buffer vco bypass logic divide by 2,4,6,8,12,16 phase frequency detector divide by 152, 160, 208 control logic charge pump m u x d a t a m u x m u x re-timer phase detector sd/hd sco_enable sco/sco clock buffer los xtal+ xtal- xtal out- xtal out+ ddi_sel[1:0] ddi 1 ddi 2 ddi 3 ddi 0 lf+ lf- kbb ddo_mute ddo/ddo autobypass bypass ld auto/man ss[2:0] asi/177 xtal osc buffer data buffer vco bypass logic divide by 2,4,6,8,12 phase frequency detector divide by 152, 160 control logic charge pump m u x d a t a m u x m u x re-timer phase detector sd/hd sco_enable sco/sco clock buffer los
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 3 of 28 revision history contents features....................................................................................................................... ..........................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 revision history ............................................................................................................... ..................................3 1. pin out..................................................................................................................... ..........................................5 1.1 GS1575B pin assignment .................................................................................................... ...........5 1.2 gs9075b pin assignment .................................................................................................... ...........6 1.3 pin descriptions .......................................................................................................... ......................7 2. electrical characteristics .................................................................................................. ....................... 10 2.1 absolute maximum ratings .................................................................................................. ..... 10 2.2 dc electrical characteristics ...... ....................................................................................... ........ 10 2.3 ac electrical characterist ics ............................................................................................. ........ 11 3. input / output circuits ..................................................................................................... ........................ 13 4. detailed description........................................................................................................ .......................... 16 4.1 slew rate phase lock loop (s-pll) ......................................................................................... 16 4.2 vco ....................................................................................................................... ............................. 17 4.3 charge pump ............................................................................................................... .................... 17 4.4 frequency acquisition loop ? the phase-frequency detector .................................. 18 4.5 phase acquisition loop ? the phase detector ................................................................... 18 4.6 4:1 input mux ............................................................................................................. ..................... 19 4.7 automatic and manual data rate selection ......................................................................... 19 4.8 bypass mode ............................................................................................................... .................... 20 4.9 dvb-asi operation ......................................................................................................... .............. 21 4.10 lock and los indicators .................................................................................................. ......... 21 4.11 output drivers and serial clock outputs ........................................................................... 22 4.12 output mute .............................................................................................................. .................... 22 5. typical application circuits ......... ....................................................................................... ................... 23 6. package & ordering information .............................................................................................. ............ 25 6.1 package dimensions ........................................................................................................ ............. 25 6.2 recommended pcb footprint .. ........... ........... ........... ........... ........... ........... ........... ........... ....... .. 26 version ecr pcn date changes and/or modifications 1 152100 ? june 2009 updated document format. 0 141777 ? august 200 6c onverting to preliminary data s heet. removed ?proprietary and c onfidential? footer. a 141210 ? july 200 6 new document.
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 4 of 28 6.3 packaging data ............................................................................................................ ................... 26 6.4 solder reflow profiles .................................................................................................... .............. 27 6.5 ordering information ...................................................................................................... ............. 28
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 5 of 28 1. pin out 1.1 GS1575B pin assignment figure 1-1: 6 4-pin qfn ddi0 gnd 64-pin qfn (top view) 1 ddi0_vtt ddi0 gnd ddi1 ddi1_vtt ddi1 gnd ddi2 ddi2_vtt ddi2 gnd ddi3 ddi3_vtt ddi3 gnd lf+ nc nc nc nc nc xtal- xtal+ xtal_out- xtal_out+ gnd vee_ddo vcc_ddo nc gnd_drv vee_sco vcc_sco sco nc gnd sco_enable sco kbb ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco locked ss0 ss1 ss2 los vcc_dig vee_dig gnd vcc_cp vee_cp asi/177 ddo ddo 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 lf- groun d pa d (bottom of pa c ka g e) nc auto/man ddo_mute sd/hd GS1575B
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 6 of 28 1.2 gs9075b pin assignment figure 1-2: 6 4-pin qfn ddi0 gnd 64-pin qfn (top view) 1 ddi0_vtt ddi0 gnd ddi1 ddi1_vtt ddi1 gnd ddi2 ddi2_vtt ddi2 gnd ddi3 ddi3_vtt ddi3 gnd lf+ nc nc nc nc nc xtal- xtal+ xtal_out- xtal_out+ gnd vee_ddo vcc_ddo nc gnd_drv vee_sco vcc_sco sco nc gnd sco_enable sco kbb ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco locked ss0 ss1 ss2 los vcc_dig vee_dig gnd vcc_cp vee_cp asi/177 ddo ddo 16 17 32 33 48 49 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 23 24 25 26 27 28 29 30 31 22 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 lf- groun d pa d (bottom of pa c ka g e) nc auto/man ? ? ? ? ddo_mute sd gs9075b ?
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 7 of 28 1.3 pin descriptions table 1-1: pin descriptions pin number name ty p e description 1, 3 ddi0, ddi0 input s erial digital differential input 0. 2 ddi0_vtt passive c enter tap of two 50 on-chip termination resistors b etween ddi0 and ddi0 . 4, 8, 12,1 6 , 32, 37, 43, 49, 6 4 g nd passive recommended connect to g nd. 5, 7 ddi1,ddi1 input s erial digital differential input 1. 6 ddi1_vtt passive c enter tap of two 50 on-chip termination resistors b etween ddi1 and ddi1 . 9, 11 ddi2, ddi2 input s erial digital differential input 2. 10 ddi2_vtt passive c enter tap of two 50 on-chip termination resistors b etween ddi2 and ddi2 . 13, 15 ddi3, ddi3 input s erial digital differential input 3. 14 ddi3_vtt passive c enter tap of two 50 on-chip termination resistors b etween ddi3 and ddi3 . 17, 18 ddi_ s el[1:0] logic input s erial digital input select. 19 bypa ss logic input bypass the reclocker stage. when bypa ss is hi g h, it overwrites the autobypa ss setting. 20 autobypa ss logic input automatically b ypasses the reclocker stage when the pll is not locked this pin is ignored when bypa ss is hi g h. 21 auto/man logic input auto/manual select. when set hi g h, the standard is automatically detected from the input data rate. when set low, the user must program the input standard using the ss [2:0] pins. 22 v cc _v c o power most positive power supply connection for the internal v c o section. c onnect to 3.3v. 23 vee_v c o power most negative power supply connection for the internal v c o section. c onnect to g nd. ddi_ s el1 ddi_ s el0 input s ele c ted 00ddi0 01ddi1 10ddi2 11ddi3
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 8 of 28 24, 25, 2 6ss [2:0] bi-directional when auto/man is hi g h, ss [0:2] are outputs, displa ying the data rate to which the pll has locked. when auto/man is low, ss [0:2] are inputs, forcing the pll to lock only to a selected data rate . 27 a s i/177 logic input when set hi g h, the device disa b les the 177m b /s data rate in the data rate detection circuit. this prevents a false lock to 177m b /s when using dvb-a s i. when set low, 177m b /s lock is possi b le, however, if a 270m b /s a s i signal is applied, the device could false lock to the 177mhz signal. 28 lo c ked output lock detect. this pin is set hi g h b y the device when the pll is locked. 29 lo s output loss of s ignal. s et hi g h when there are no transitions on the active ddi[3:0] input. s ee lock and lo s indicators on page 21 . 30 v cc _di g power most positive power supply conn ection for the internal glue logic. c onnect to 3.3v. 31 vee_di g power most negative power supply connection for th e internal glue logic. c onnect to g nd. 33 s d/hd ( gs 1575b only) output this signal will b e set low b y the device when the reclocker has locked to 1.485 gb ps or 1.485/1.001 gb ps, or when a non- s mpte standard is applied (i.e. the device is not locked). it will b e set hi g h when the reclocker has locked to 143m b ps, 177m b ps, 270m b ps, 3 6 0m b ps, or 540m b ps. 33 s d ( gs 9075b only) output this signal will go hi g h when the reclocker has locked to the input s d signal. it will b e low otherwise. 34 kbb analog input c ontrols the loop b andwidth of the pll. leave this pin floating for se rial reclocking applications. 35 sc o_enable power s erial clock output ena b le. c onnect to v cc to ena b le the serial clock output. c onnect to g nd to disa b le the serial clock output. note: this is not a ttl signal input. 3 6 ddo_mute logic input mutes the ddo/ddo outputs. this option is not availa b le in b ypass mode. table 1-1: pin descriptions (continued) pin number name ty p e description ss 2 ss 1 ss 0 data rate s ele c ted/for c ed (m b /s) 0 0 0 143 0 0 1 177 0 1 0 270 011 3 6 0 1 0 0 540 1 0 1 1483.5/1485
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 9 of 28 38, 40 sc o , sc o output s erial clock output. when sc o_enable is set hi g h, a serial digital differential clock will b e presented to the application layer at the selected data rate. 39, 45, 54 - 59 n c no c onnect not connected internally. 41 v cc _ sc o power most positive power supply connection for the sc o/ sc o output driver. c onnect to 3.3v. 42 vee_ sc o power most negative power supply connec tion for the sc o/ sc o output driver. c onnect to g nd. 43 g nd_drv passive recommended connect to g nd. 44, 4 6 ddo , ddo output differential s erial digital outputs. 47 v cc _ddo power most positive power supply connection for the ddo/ddo output driver. c onnect to 3.3v. 48 vee_ddo power most negative power supply connection for the ddo/ddo output driver. c onnect to g nd. 50, 51 xtal_out+, xtal_out- output differential outputs of the referenc e oscillator used for monitoring or test purposes. 52, 53 xtal+, xtal- input reference crystal input. c onnect to the g o1535 as shown in the typical application c ircuits on page 23 . 6 0 vee_ c p power most negative power supply conn ection for the internal charge pump. c onnect to g nd. 6 1v cc _ c p power most positive power supply connecti on for the internal charge pump. c onnect to 3.3v. 6 2, 6 3 lf+, lf- passive loop filter capacitor connection. c onnect as shown in the typical application c ircuits on page 23 . ? c enter pad ? g round pad on b ottom of package. s older to main ground plane following recommendations under recommended p c b footprint on page 2 6 . table 1-1: pin descriptions (continued) pin number name ty p e description
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 10 of 28 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value s upply voltage +3. 6 v d c input voltage vcc + 0.5v operating temperature range 0 c to 70 c s torage temperature range -50 c < t s < 125 c input e s d voltage 1kv s older reflow temperature 2 6 0 c table 2-1: dc electrical characteristics v cc = 3.3v, t a = 0 c to 70 c , unless otherwise shown parameter symbol conditions min ty p max units s upply voltage v cc operating range 3.135 3.3 3.4 6 5v s upply c urrent i cc sc o ena b led, t a =25 c ? 215 2 6 0ma i cc sc o disa b led, t a =25 c ? 195 230 ma power c onsumption ? sc o ena b led, t a =25 c ? 710 ? mw ? sc o disa b led, t a =25 c ? 6 45 ? mw logic inputs ddi_ s el[1:0], bypa ss , autobypa ss , auto/man , a s i/177 , ddo_mute v ih high 2.0 ? ? v v il low ? ? 0.8 v logic outputs s d/hd , lo c ked, lo s v oh 250ua load 2.8 ? ? v v ol 250ua load ? ? 0.5 v bi-directional pins (manual mode) ss [2:0], auto/man = 0 v ih high 2.0 ? ? v v il low ? ? 0.8 v
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 11 of 28 2.3 ac electrical characteristics bi-directional pins (auto mode) ss [2:0], auto/man = 1 v oh high, 250ua load 2.8 ? ? v v ol low, 250ua load ? ? 0.5 v xtal_out+, xtal_out- v oh high ? v cc ?v v ol low ? v cc - 0.285 ? v sc o_enable ? 1.5ma of current delivered v cc - 0.1 6 5? v cc + 0.1 6 5v s erial input voltage ? c ommon mode 1. 6 5 + (v s id /2) ?v cc - (v s id /2) v s erial output voltage s do/ s do , sc o/ sc o ? c ommon mode ? v cc - (v od /2) ? v table 2-1: dc electrical characteristics (continued) v cc = 3.3v, t a = 0 c to 70 c , unless otherwise shown parameter symbol conditions min ty p max units table 2-2: ac electrical characteristics v cc = 3.3v, t a = 0 c to 70 c , unless otherwise shown parameter symbol conditions min ty p max units s erial input data rate ? gs 1575b 143 ? 1485 m b /s ? gs 9075b 143 ? 540 m b /s s erial input jitter tolerance ? worst case modulation (e.g. square wave modulation) 143, 270, 3 6 0, 1485 m b /s 0.8 ? ? ui pll lock time - asynchronous t alo c k ???10ms pll lock time - s ynchronous t s lo c k c lf =47nf, s d/hd =0 ? ? 10 us t s lo c k c lf =47nf, s d/hd =1 ? ? 39 us s erial output rise/fall time s do/ s do and sc o/ sc o (20% - 80%) t r s do ,t r sc o 50 load (on chip) ? 114 ? ps t f s do ,t f sc o 50 load (on chip) ? 10 6 ?ps s erial digital input s ignal s wing v s id differential with internal 100 input termination s ee figure 2-1 100 ? 800 mv p-p s erial digital output s ignal s wing s do/ s do and sc o/ sc o v od 100 load differential s ee figure 2-2 1400 1 6 00 2200 mv p-p
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 12 of 28 figure 2-1: s erial digital input s ignal s wing figure 2-2: s erial digital output s ignal s wing s erial output jitter s do/ s do and sc o/ sc o kbb = float prn, 2 23 -1 measurement is output jitter that includes input jitter from bert. t oj 143 m b /s ? 0.02 ? ui t oj 177 m b /s ? 0.02 ? ui t oj 270 m b /s ? 0.02 0.09 ui t oj 3 6 0 m b /s ? 0.03 ? ui t oj 540 m b /s ? 0.03 0.09 ui t oj 1485 m b /s ( gs 1575b only) ? 0.0 6 0.13 ui t oj bypass ? 0.0 6 0.13 ui loop bandwidth bw loop 1.485 gb /s, kbb = float ( gs 1575b only) ?1.75?mhz bw loop 1.485 gb /s, kbb = g nd, <0.1db peaking ( gs 1575b only) ?3.2?mhz bw loop 270 m b /s, kbb = float ? 520 ? khz bw loop 270 m b /s, kbb = g nd ? 1000 ? khz table 2-2: ac electrical characteristics (continued) v cc = 3.3v, t a = 0 c to 70 c , unless otherwise shown parameter symbol conditions min ty p max units v s id v s id 2 v s id 2 v s id 2 + 0 v s id 2 _ v s id 2 v cc _ v s id 2 v cc _ v cc v dd s ingle-ended s wing (ddix) s ingle-ended s wing (ddix) differential s wing (ddix-ddix) v od v od 2 v od 2 v od 2 + 0 v od 2 _ v od 2 v cc _ v od 2 v cc _ v cc v dd s ingle-ended s wing (ddo, sc o) s ingle-ended s wing (ddo, sc o) differential s wing (ddo-ddo) ( sc o- sc o)
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 13 of 28 3. input / output circuits figure 3-1: ttl inputs figure 3-2: loop filter figure 3-3: c rystal input v ref lf+ lf- 5k 10p 250r 250r 5k xtal+ xtal-
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 14 of 28 figure 3-4: c rystal output buffer figure 3-5: s erial data outputs, s erial c lock outputs figure 3- 6 : kbb figure 3-7: indicator outputs: s d/ hd , lo c ked, lo s 1k 1k xtal out- xtal out+ 50 sdo/sco sdo/sco 50 500r v ref kbb
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 15 of 28 figure 3-8: s tandard s elect/indication bi-directional pins figure 3-9: s erial data inputs v ref ss[2:0] 50 ddi[3:0] ddi[3:0] 1k 1k 50 ddi_vtt
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 16 of 28 4. detailed description the GS1575B/9075b is a multi-rate serial digi tal reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. the GS1575B will recover the embedded clock signal and re-time the data from a smpte 292m, smpte 259m or smpte 344m co mpliant digital video signal. the gs9075b will recover the embedded clock signal and re-time the data from a smpte 259m or smpte 344m compliant digita l video signal. using the functional block diagram ( page 2 ) as a guide, slew rate phase lock loop (s-pll) on page 16 to output mute on page 22 describes each aspect of the GS1575B/9075b in detail. 4.1 slew rate phase lock loop (s-pll) the term ?slew? refers to the output phase of the pll in response to a step change at the input. linear plls have an output phase response characterized by an exponential response whereas an s-pll?s output is a ramp response (see figure 4-1 ). because of this non-linear response characteristic, traditional small signal analysis is not possible with an s-pll. figure 4-1: pll c haracteristics 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui)
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 17 of 28 the s-pll offers several advantages over th e linear pll. the loop bandwidth of an s-pll is independent of the transition density of the input data. pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. the loop bandwidth of a linear pll will change proportionally with this change in transition density. with an s-pll, the loop bandwidth is defined by the jitter at the data input. this translates to infinite loop bandwidth with a zero jitter input signal. this allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. the loop bandwidth of th e GS1575B/9075b?s pll is defined at 0.2ui of input jitter. the pll consists of two acquisition loops. first is the frequency acquisition (fa) loop. this loop is active when the device is not locked and is used to achieve lock to the supported data rates. second is the phase acquisition (pa) loop. once locked, the pa loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 vco the internal vco of the GS1575B/9075b is a ring oscillator. it is tr immed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. integrated into the vco is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 charge pump a common charge pump is used for the pll of the GS1575B/9075b. during frequency acquisition, the charge pump has two states, ?pump-up? and ?pump-down,? which is produced by a leading or lagging phase difference between the input and the vco frequency. during phase acquisition, there are two levels of ?pump-up? and two levels of ?pump down? produced for leading and lagging phase difference between the input and vco frequency. this is to allow for greater precision of vco control. the charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, c lf . the instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor.
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 18 of 28 4.4 frequency acquisit ion loop the phase-frequency detector an external crystal of 14.140 mhz is used as a reference to keep the vco centered at the last known data rate. this allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. the crystal reference is also used to clock internal timers and counters. to keep the optimal performance of the reclocker over all operatin g conditions, the crystal fr equency must be 14.140 mhz, +/-50ppm. the go1535 meets this specif ication and is avai lable from gennum. the vco is divided by a selected ratio which is dependant on the input data rate. the resultant is then compared to the crystal frequency. if the divided vco frequency and the crystal frequency are within 1% of each ot her, the pll is considered to be locked to the input data rate. 4.5 phase acquisition lo op the phase detector the phase detector is a digital quadrature ph ase detector. it indicates whether the input data is leading or lagging with respect to a clock that is in phase with the vco (i-clk) and a quadrature clock (q-clk). when the phase acquisition loop (pa loop) is locked, the input data transition is aligned to the falling edge of i-clk and the output data is re-timed on the rising edge of i-clk. during high input jitter conditions (>0.25ui), q-clk will sample a different value than i-clk. in this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the vco. figure 4-2: phase detector c haracteristics when the pa loop is active, the crystal frequency and the incoming data rate are compared. if the resultant is more that 2%, the pll is considered to be unlocked and the system jumps to the fa loop. i-phase alignment edge data re-timing edge q -phase alignment edge 0.25ui 0.8ui i- c lk q - c lk input data with j itter re-timed output data
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 19 of 28 4.6 4:1 input mux the 4:1 input mux allows the connection of four independent streams of video/data. there are four differential inputs (ddi[3:0] and ddi[3:0] ). the active channel can be selected via the ddi_sel[1:0] pins. table 4-1 shows the input selected for a given state at ddi_sel[1:0]. the ddi inputs are designed to be dc inte rfaced with the output of the gs1524a/9064a cable equalizer. there are on chip 50 termination resistors which come to a common point at the ddi_vt pins. connect a 10nf capacitor to this pin and connect the other end of the capacitor to ground. this terminates the transmission line at the inputs for optimum performance. if only one input pair is used, connect the unused positive inputs to +3.3v and leave the unused negative inputs floating. this helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 automatic and manual data rate selection the GS1575B/9075b can be configured to manua lly lock to a specif ic data rate or automatically search for and lock to the incoming data rate. the auto/man pin selects automatic data rate detection mode (auto mode) when high and manual data rate selection mode (manual mode) when low. in auto mode, the ss[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the pll is locked to (or previously locked to). the "search algorithm" cycles through the data rates and starts over if that data rate is not found (see figure 4-3 ). figure 4-3: data rate s earch pattern table 4-1: bit pattern for input select ddi_sel[1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3 143 mb/s 177 mb/s 270mb/s 360 mb/s 540 mb/s power-up 1.485mb/s (GS1575B only)
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 20 of 28 in manual mode, the ss[2:0] pins become i nputs and the data rate can be programmed by the application layer. in this mode, the search algorithm is disabled and the pll will only lock to the da ta rate selected. table 4-2 shows the ss[2:0] pin settings for either the data rate selected (in manual mode) or the data rate that the pll has locked to (in auto mode). 4.8 bypass mode in bypass mode, the GS1575B/9075b passes the data at the inputs directly to the outputs. there are two pins that control the by pass function: bypass and autobypass. when bypass is set high by the applic ation layer, the gs 1575b/9075b will be in bypass mode. when autobypass is set high by the application layer, the GS1575B/9075b will be configured to enter bypass mode only when the pll has not locked to a data rate. when bypass is set high, auto bypass will be ignored. when the pll is not locked, and both bypa ss and autobypass are set low, the serial digital output ddo/ddo will produce invalid data. table 4-2: data rate indi cation/selecti on bit pattern ss[2:0] data rate (mb/s) 000 143 001 177 010 270 011 3 6 0 100 540 101* 1485/1483.5 * this setting only applies to the gs 1575b. for the gs 9075b, when auto/man is low, the pin settings ss [0:2] = 101 will b e ignored b y the device.
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 21 of 28 4.9 dvb-asi operation the GS1575B/9075b will also re -clock dvb-asi at 270 mb/s . when reclocking dvb-asi data set the asi/177 pin high to prevent a false lock to 177mb/s. if asi/177 is not set high, a false lock may occur since there is a harmonic present in idle patterns (k28.5) which is very close the 177 mb/s data rate (eic 1179) . note that setting the asi/177 pin high will disable the 177 mb/s search when the device is in auto mode, consequently the GS1575B/9075b will not lock to that data rate. 4.10 lock and los indicators the locked signal is an active high outp ut which indicates when the pll is locked. the internal lock logic of the GS1575B/9075b includes a system which monitors the frequency acquisition loop and the phase acquisition loop as well as a monitor to detect harmonic lock. the los (loss of signal) output is an active high output which indicates the absence of data transitions at the ddix input. in order for this output to be asserted, transitions must not be present for a period of typically 5.14 us. after this output has been asserted, los will deassert typically 5.14 us after the appearance of a transition at the ddix input. this timing relationship is shown in figure 4-4 : figure 4-4: lo s signal timing note: los is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. data lo s 5.14 us 5.14 us
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 22 of 28 4.11 output drivers an d serial clock outputs the device?s serial digi tal data outputs (ddo/ddo ) have a nominal voltage of 800mv single ended or 1600mv differentia l when terminated into a 50 load . the GS1575B/9075b may also be configured to output a serial clock at the data output rate. the internal serial clock output block is powered via the sco_enable pin. when sco_enable is connected to vcc, a differential serial clock output will be present on sco/sco . otherwise, when sco_enable is connected to gnd, the clock output block will be powered down and the device will have reduced power consumption. note: the sco_enable signal should have a 1.5ma drive strength to maintain a supply voltage of 3.3 +/- 0.165v. clock and data alignment is shown in figure 4-5 . figure 4-5: c lock and data alignment 4.12 output mute the ddo_mute pin is provided to allow muting of the re-timed output. when the pll is locked and the device is reclocking, setting ddo_mute = low will force the serial digital outputs ddo/ddo to mute. however, if the GS1575B/9075b is in bypass mode, (autobypass = high and/or bypass = high), ddo_mute will have no effect on the output. data sc lk t c d for hd- s di: t c d = 32ps (typ.), 3 6 ps (max.) for s d- s di: t c d = 30ps (typ.), 38ps (max.)
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 23 of 28 5. typical application circuits figure 5-1: gs 1575b typical application c ircuit asi_177 ddi_sel1 sdo_mute ddi_sel0 locked sd/hd 3.3v 3.3v 3.3v 3.3v 10n 10n 10n 10n 47n GS1575B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ddi0 ddi0_vt ddi0 gnd ddi1 ddi1_vt ddi1 gnd ddi2 ddi2_vt ddi2 gnd ddi3 ddi3_vt ddi3 gnd ddi_sel0 ddi_sel1 bypass autobypass auto/man vcc_vco vee_vc0 ss0 ss1 ss2 asi/177 locked los vcc_dig vee_dig gnd sd/hd kbb sco_enable ddo_mute gnd nc sco vcc_sco vee_sco gnd ddo nc ddo vcc_ddo vee_ddo gnd xtal_out+ xtal_out- xtal+ xtal- nc vee_cp vcc_cp lf- lf+ gnd 10n (14.140mhz) 10n 10n 10n data input 1 data input 0 data input 3 data input 2 data output zo = 50 zo = 50 zo = 50 zo = 50 zo = 50 3.3v 10n 100 go1535 note: all resistors in ohms an d all c apa c itors in fara d s. nc nc nc nc nc sco clock output zo = 50 los
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 24 of 28 figure 5-2: gs 9075b typical application c ircuit asi_177 ddi_sel1 sdo_mute ddi_sel0 locked sd 3.3v 3.3v 3.3v 3.3v 10n 10n 10n 10n 47n gs9075b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ddi0 ddi0_vt ddi0 gnd ddi1 ddi1_vt ddi1 gnd ddi2 ddi2_vt ddi2 gnd ddi3 ddi3_vt ddi3 gnd ddi_sel0 ddi_sel1 bypass autobypass auto/man vcc_vco vee_vc0 ss0 ss1 ss2 asi/177 locked los vcc_dig vee_dig gnd sd kbb sco_enable ddo_mute gnd nc sco vcc_sco vee_sco gnd ddo nc ddo vcc_ddo vee_ddo gnd xtal_out+ xtal_out- xtal+ xtal- nc vee_cp vcc_cp lf- lf+ gnd 10n (14.140mhz) 10n 10n 10n data input 1 data input 0 data input 3 data input 2 data output zo = 50 zo = 50 zo = 50 zo = 50 zo = 50 3.3v 10n 100 go1535 note: all resistors in ohms an d all c apa c itors in fara d s. nc nc nc nc nc sco clock output zo = 50 los
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 25 of 28 6. package & ordering information 6.1 package dimensions a b 9.00 4.50 4.50 9.00 2x 2x 0.15 c 0.15 c 0.10 c 0.08 c 64x seating plane 0.90 +/- 0.10 +0.03 0.02-0.02 0.20 ref c 7.10+/-0.15 3.55 0.40+/-0.05 7.10+/-0.15 3.55 0.25+/-0.05 64x 0.10 c ab c 0.05 0.50 all dimensions in mm pin 1 area centre tab 45 45
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 26 of 28 6.2 recommended pcb footprint the center pad of the pcb footprint should be connected to the ground plane by a minimum of 36 vias. note: suggested dimensions only. final dimensions shou ld conform to customer design rules and process optimizations. 6.3 packaging data note: all dimensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 c enter pad parameter value package type 9mm x 9mm 6 4-pin qfn moisture s ensitivity level 3 junction to c ase thermal resistance, j-c 9.1 c /w junction to air thermal resistance, j-a (at zero airflow) 21.5 c /w psi, 0.2 c /w p b -free and roh s c ompliant yes
GS1575B / gs9075b hd-linx? ii multi-rate sdi automatic reclocker data sheet 40063 - 1 june 2009 27 of 28 6.4 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. msl qualification was performed using the maximum pb-free solder reflow profile shown in figure 6-1 . the recommended standard pb solder reflow profile is shown in figure 6-2 . figure 6 -1: maximum p b -free s older reflow profile (preferred) figure 6 -2: s tandard p b s older reflow profile 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 se c . max 60-150 se c . 20-40 se c . 3c/se c max 6c/se c max 25c 100c 150c 183c 230c 220c time temperature 6 min. max 120 se c . max 60-150 se c . 10-20 se c . 3c/se c max 6c/se c max
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